diff --git a/src/drivers/stm32/drv_led_pwm.cpp b/src/drivers/stm32/drv_led_pwm.cpp
index 8e9f914b363194f63c923d15323d74815f8595c7..c9eafb239171c01f1b11db60433de7963b0412be 100644
--- a/src/drivers/stm32/drv_led_pwm.cpp
+++ b/src/drivers/stm32/drv_led_pwm.cpp
@@ -116,49 +116,52 @@ led_pwm_timer_get_period(unsigned timer)
 
 static void led_pwm_timer_init_timer(unsigned timer)
 {
-	irqstate_t flags = px4_enter_critical_section();
+	if (led_pwm_timers[timer].base) {
 
-	/* enable the timer clock before we try to talk to it */
+		irqstate_t flags = px4_enter_critical_section();
 
-	modifyreg32(led_pwm_timers[timer].clock_register, 0, led_pwm_timers[timer].clock_bit);
+		/* enable the timer clock before we try to talk to it */
 
-	/* disable and configure the timer */
-	rCR1(timer) = 0;
-	rCR2(timer) = 0;
-	rSMCR(timer) = 0;
-	rDIER(timer) = 0;
-	rCCER(timer) = 0;
-	rCCMR1(timer) = 0;
-	rCCMR2(timer) = 0;
-	rCCR1(timer) = 0;
-	rCCR2(timer) = 0;
-	rCCR3(timer) = 0;
-	rCCR4(timer) = 0;
-	rCCER(timer) = 0;
-	rDCR(timer) = 0;
+		modifyreg32(led_pwm_timers[timer].clock_register, 0, led_pwm_timers[timer].clock_bit);
 
-	if ((led_pwm_timers[timer].base == STM32_TIM1_BASE) || (led_pwm_timers[timer].base == STM32_TIM8_BASE)) {
+		/* disable and configure the timer */
+		rCR1(timer) = 0;
+		rCR2(timer) = 0;
+		rSMCR(timer) = 0;
+		rDIER(timer) = 0;
+		rCCER(timer) = 0;
+		rCCMR1(timer) = 0;
+		rCCMR2(timer) = 0;
+		rCCR1(timer) = 0;
+		rCCR2(timer) = 0;
+		rCCR3(timer) = 0;
+		rCCR4(timer) = 0;
+		rCCER(timer) = 0;
+		rDCR(timer) = 0;
 
-		/* master output enable = on */
+		if ((led_pwm_timers[timer].base == STM32_TIM1_BASE) || (led_pwm_timers[timer].base == STM32_TIM8_BASE)) {
 
-		rBDTR(timer) = ATIM_BDTR_MOE;
-	}
+			/* master output enable = on */
+
+			rBDTR(timer) = ATIM_BDTR_MOE;
+		}
 
-	/* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
-	 * then configure the timer to free-run at 1MHz.
-	 * Otherwise, other frequencies are attainable by adjusting .clock_freq accordingly.
-	 */
+		/* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
+		 * then configure the timer to free-run at 1MHz.
+		 * Otherwise, other frequencies are attainable by adjusting .clock_freq accordingly.
+		 */
 
-	rPSC(timer) = (led_pwm_timers[timer].clock_freq / 1000000) - 1;
+		rPSC(timer) = (led_pwm_timers[timer].clock_freq / 1000000) - 1;
 
-	/* configure the timer to update at the desired rate */
+		/* configure the timer to update at the desired rate */
 
-	rARR(timer) = (1000000 / LED_PWM_RATE) - 1;
+		rARR(timer) = (1000000 / LED_PWM_RATE) - 1;
 
-	/* generate an update event; reloads the counter and all registers */
-	rEGR(timer) = GTIM_EGR_UG;
+		/* generate an update event; reloads the counter and all registers */
+		rEGR(timer) = GTIM_EGR_UG;
 
-	px4_leave_critical_section(flags);
+		px4_leave_critical_section(flags);
+	}
 
 }
 #endif