From 1f5421422487affc78d2e10db26c7303f827c667 Mon Sep 17 00:00:00 2001
From: David Sidrane <david_s5@nscdg.com>
Date: Thu, 29 Nov 2018 12:42:16 -0800
Subject: [PATCH] stm32/drv_io_timer:GTIM_CCER_CC1NP not on all STM32 HW

   The F1 series GTIMs to not have GTIM_CCER_CC1NP.
   This bug fix tracks the upstream change that
   made GTIM_CCER_CC1NP conditional on the chip.
---
 src/drivers/stm32/drv_io_timer.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/drivers/stm32/drv_io_timer.c b/src/drivers/stm32/drv_io_timer.c
index 1b1471d4c2..2c1634e633 100644
--- a/src/drivers/stm32/drv_io_timer.c
+++ b/src/drivers/stm32/drv_io_timer.c
@@ -63,6 +63,12 @@
 #include <stm32_gpio.h>
 #include <stm32_tim.h>
 
+#if defined(HAVE_GTIM_CCXNP)
+#define HW_GTIM_CCER_CC1NP GTIM_CCER_CC1NP
+#else
+#  define HW_GTIM_CCER_CC1NP    0
+#endif
+
 #define arraySize(a) (sizeof((a))/sizeof(((a)[0])))
 
 /* If the timer clock source provided as clock_freq is the STM32_APBx_TIMx_CLKIN
@@ -729,7 +735,7 @@ int io_timer_channel_init(unsigned channel, io_timer_channel_mode_t mode,
 
 		/* on PWM Out ccer_setbits is 0 */
 
-		clearbits = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP) << (shifts * CCER_C1_NUM_BITS);
+		clearbits = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | HW_GTIM_CCER_CC1NP) << (shifts * CCER_C1_NUM_BITS);
 		setbits  = ccer_setbits << (shifts * CCER_C1_NUM_BITS);
 		rvalue = rCCER(timer);
 		rvalue &= ~clearbits;
-- 
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