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Commit 6b6aa9ed authored by Daan Bijl's avatar Daan Bijl
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update demo setup initialisation to compatible with current core-tools version

parent ea8fe5a3
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......@@ -4,30 +4,42 @@ import os
import setup_config
from setup_config.setup_hardware import setup_hardware
from core_tools.GUI.keysight_videomaps.data_getter.scan_generator_Virtual import fake_digitizer
from pulse_lib.tests.mock_m3202a import MockM3202A
def init_station():
def init_station():
# load config file with the instrument settings
station = qcodes.Station(config_file = os.path.dirname(setup_config.__file__) + '\\instruments.yaml')
instrument_config_path = os.path.join(
os.path.dirname(setup_config.__file__),
'instruments.yaml'
)
station = qcodes.Station(config_file=instrument_config_path)
station.load_instrument('D5a1')
station.load_instrument('D5a2')
station.load_instrument('D5a3')
# station.load_instrument('D5a1', spi_rack=None)
# station.load_instrument('D5a2', spi_rack=None)
# station.load_instrument('D5a3', spi_rack=None)
# station.load_instrument('D5a1', spi_rack=None)
# station.load_instrument('D5a2', spi_rack=None)
# station.load_instrument('D5a3', spi_rack=None)
hw = setup_hardware()
station.add_component(hw)
station.load_instrument(
'gates', hardware = hw,
dac_sources = [station.D5a1, station.D5a2, station.D5a3])
'gates',
hardware=hw,
dac_sources=[
station.D5a1,
station.D5a2,
station.D5a3
]
)
# load the digitizer
# station.load_instrument('digitizer_keys')
dig = fake_digitizer('digitizer_keys')
dig = MockM3202A(
name="Dig1",
chassis=1,
slot=11
)
station.add_component(dig)
station.load_instrument('AWG1')
......
......@@ -33,6 +33,26 @@ instruments:
chassis: 1
slot: 11
sig_gen1:
type: qcodes.instrument_drivers.mock_instruments.DummyInstrument
# type: qcodes.tests.instrument_mocks.DummyInstrument
enable_forced_reconnect: true
init:
gates: ['frequency','power']
parameters:
frequency:
limits: [0,20e9]
sig_gen2:
type: qcodes.instrument_drivers.mock_instruments.DummyInstrument
# type: qcodes.tests.instrument_mocks.DummyInstrument
enable_forced_reconnect: true
init:
gates: ['frequency','power']
parameters:
frequency:
limits: [0,20e9]
AWG1:
type: pulse_lib.tests.mock_m3202a.MockM3202A_fpga
enable_forced_reconnect : True
......@@ -66,8 +86,8 @@ instruments:
enable_forced_reconnect : True
init:
chassis : 1
slot : 6
slot : 6
AWG6:
type: pulse_lib.tests.mock_m3202a.MockM3202A_fpga
enable_forced_reconnect : True
......@@ -80,11 +100,25 @@ instruments:
enable_forced_reconnect : True
init:
chassis : 1
slot : 8
slot : 8
AWG8:
type: pulse_lib.tests.mock_m3202a.MockM3202A_fpga
enable_forced_reconnect : True
init:
chassis : 1
slot : 9
slot : 9
Dig1:
type: pulse_lib.tests.mock_m3102a.MockM3102A
enable_forced_reconnect: true
init:
chassis: 1
slot: 11
Dig2:
type: pulse_lib.tests.mock_m3102a.MockM3102A
enable_forced_reconnect: true
init:
chassis: 1
slot: 12
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