* drivers, magnetometer: added ak09916 driver to support the mag driver emulated by the Here2 gps
* boards: set yaw 270 rotation for external ak09916 driver and only start it for the PH21
* drivers: only start ak09916 when icm20948 is not available on a ph21 setup

   Addresses #11832 - configure the mixed use GPIO
   that can be the a BLue LED or a Heater as PUSH
   PULL on Cube as to not let the heater input float.

Add back pwm out sim module so HITL simulation works again.

* Support for armv7-m_dcache control via parameter

  The FORCE_F7_DCACHE parameter can be set to
   0 - (default) if Eratta exits turn dcache off else leave it on
   1 -  Force it off
   2 -  Force it on

   At boot the system will disable the d-cache if the silicon
   has the 1259864 Data corruption in a sequence of Write-Through
   stores and loads eratta.

   Post nsh script execution the FORCE_F7_DCACHE paramater
   will be used to set the d-cache to the state indicated
   above.

Delete trailing whitespace, extra newlines, to quiet git hooks and add an extra = so that it does not appear to git as a merge conflict marker.

The replay functionality was broken with lockstep. This is an interim
fix for the replay functionality.

In the longer term it would be nice to leverage the lockstep speedup
for the replay.

 * working debugging (one click build and debug)
   * SITL jmavsim
   * SITL gazebo
   * jlink px4_fmu-v{2-5}
 * improved syntax highlighting
   * GNU linker files
   * ROS message files msg/*.msg
   * jinja2 template files
 * fixed intellisense support

   This also fixes a typo in the GPIO defines

   The cause of the stack detection fault is because of the
   level of nesting in the start up script. We need to
   determine the worst case configuration and set the
   bar there.

   This fault occurred some 42 calls deep due to script
   calling script (repeat).

   The HW stack check requires as a margin of 204 bytes. That is
   ISR HW stacking of CPU(8) FPU(18) registers and SW stacking of
   CPU(11) and FPU(16) registers. Total CPU(19) registers is
   68 bytes and the total FPU(34) registers is 136 bytes.  On
   a system with a separate ISR stack This only needs to be 104
   so there is 100 bytes of headroom. But as coded the detection
   will give a false positive detection and fault. This does not
   mean that the stack will be corrupted.

   Adjustments to that stack can have no effect due to rounding.
   A stack size of 2608 and 2616 can yield the exact same size stack.
   So even when the failure is due to a 4 byte overflow, it can take
   greater than a 16 bytes increase to fix it. Because the final
   stack size is calculated with an 8 byte alignment after a 4 byte
   decrease. So 2624 becomes 2620 at runtime and will boot
   with SYS_AUTOSTART=4001.

   nARMED is a Digital OUTPUT. GPIO will be set as input while not
   armed HW will have Pull UP. While armed it will be configured
   as a GPIO OUT set LOW.

 - see 1259864 Data corruption in a sequence of Write-Through stores and loads
 - if we can be certain this sequence won't occur in PX4 then the d-cache will be re-enabled

 - update navigator precision landing to build without multicopter