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  1. Apr 02, 2019
    • David Sidrane's avatar
      [Breaking Change]fmuk66-v3: Only Support Rev BX11 · ef882989
      David Sidrane authored
         I2C bus chaged I2C0 is external, I2C1 internal
           Added BMM150 on I2C1 @ Addr 0x100
           Added BMP280 on I2C1 @ Addr 0x76
      
         UART0 (/dev/ttyS1) now used at Telem 2
      
         Chip select added for W25X40CLUXIG Calibration EE prom
           Driver is not added at this time
      ef882989
  2. Mar 27, 2019
    • Julian Oes's avatar
      SITL: interim fix for replay · 187f3f28
      Julian Oes authored
      The replay functionality was broken with lockstep. This is an interim
      fix for the replay functionality.
      
      In the longer term it would be nice to leverage the lockstep speedup
      for the replay.
      187f3f28
  3. Mar 24, 2019
  4. Mar 23, 2019
    • Daniel Agar's avatar
      vscode updates · 5e6bfe1a
      Daniel Agar authored
       * working debugging (one click build and debug)
         * SITL jmavsim
         * SITL gazebo
         * jlink px4_fmu-v{2-5}
       * improved syntax highlighting
         * GNU linker files
         * ROS message files msg/*.msg
         * jinja2 template files
       * fixed intellisense support
      Unverified
      5e6bfe1a
  5. Mar 21, 2019
  6. Mar 18, 2019
  7. Mar 16, 2019
  8. Mar 15, 2019
  9. Mar 12, 2019
  10. Mar 11, 2019
  11. Mar 02, 2019
    • mcsauder's avatar
    • David Sidrane's avatar
      board:Set larger stack margin · edd9f91a
      David Sidrane authored
      edd9f91a
    • David Sidrane's avatar
      px4_fmuv5:Stack Check build Increase to 2624 · 12d442e8
      David Sidrane authored
         The cause of the stack detection fault is because of the
         level of nesting in the start up script. We need to
         determine the worst case configuration and set the
         bar there.
      
         This fault occurred some 42 calls deep due to script
         calling script (repeat).
      
         The HW stack check requires as a margin of 204 bytes. That is
         ISR HW stacking of CPU(8) FPU(18) registers and SW stacking of
         CPU(11) and FPU(16) registers. Total CPU(19) registers is
         68 bytes and the total FPU(34) registers is 136 bytes.  On
         a system with a separate ISR stack This only needs to be 104
         so there is 100 bytes of headroom. But as coded the detection
         will give a false positive detection and fault. This does not
         mean that the stack will be corrupted.
      
         Adjustments to that stack can have no effect due to rounding.
         A stack size of 2608 and 2616 can yield the exact same size stack.
         So even when the failure is due to a 4 byte overflow, it can take
         greater than a 16 bytes increase to fix it. Because the final
         stack size is calculated with an 8 byte alignment after a 4 byte
         decrease. So 2624 becomes 2620 at runtime and will boot
         with SYS_AUTOSTART=4001.
      12d442e8
  12. Feb 26, 2019
  13. Feb 25, 2019
  14. Feb 19, 2019
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