- Mar 21, 2019
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Daniel Agar authored
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Daniel Agar authored
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Daniel Agar authored
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Daniel Agar authored
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Daniel Agar authored
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Daniel Agar authored
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Daniel Agar authored
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Daniel Agar authored
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Daniel Agar authored
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Daniel Agar authored
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Daniel Agar authored
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- Mar 18, 2019
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David Sidrane authored
This also fixes a typo in the GPIO defines
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- Mar 16, 2019
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Daniel Agar authored
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- Mar 15, 2019
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Hamish Willee authored
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- Mar 12, 2019
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Claudio Micheli authored
Signed-off-by:
Claudio Micheli <claudio@auterion.com>
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baumanta authored
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baumanta authored
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baumanta authored
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- Mar 11, 2019
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Vasily Evseenko authored
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- Mar 02, 2019
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mcsauder authored
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David Sidrane authored
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David Sidrane authored
The cause of the stack detection fault is because of the level of nesting in the start up script. We need to determine the worst case configuration and set the bar there. This fault occurred some 42 calls deep due to script calling script (repeat). The HW stack check requires as a margin of 204 bytes. That is ISR HW stacking of CPU(8) FPU(18) registers and SW stacking of CPU(11) and FPU(16) registers. Total CPU(19) registers is 68 bytes and the total FPU(34) registers is 136 bytes. On a system with a separate ISR stack This only needs to be 104 so there is 100 bytes of headroom. But as coded the detection will give a false positive detection and fault. This does not mean that the stack will be corrupted. Adjustments to that stack can have no effect due to rounding. A stack size of 2608 and 2616 can yield the exact same size stack. So even when the failure is due to a 4 byte overflow, it can take greater than a 16 bytes increase to fix it. Because the final stack size is calculated with an 8 byte alignment after a 4 byte decrease. So 2624 becomes 2620 at runtime and will boot with SYS_AUTOSTART=4001.
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- Feb 26, 2019
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David Sidrane authored
nARMED is a Digital OUTPUT. GPIO will be set as input while not armed HW will have Pull UP. While armed it will be configured as a GPIO OUT set LOW.
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- Feb 25, 2019
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fpvaspassion authored
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Mohammed Kabir authored
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- Feb 19, 2019
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Beat Küng authored
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Beat Küng authored
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DanielePettenuzzo authored
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- Feb 18, 2019
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Daniel Agar authored
- see 1259864 Data corruption in a sequence of Write-Through stores and loads - if we can be certain this sequence won't occur in PX4 then the d-cache will be re-enabled
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- Feb 13, 2019
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David Sidrane authored
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- Feb 11, 2019
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Daniel Agar authored
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David Sidrane authored
- see 1259864 Data corruption in a sequence of Write-Through stores and loads - if we can be certain this sequence won't occur in PX4 then the d-cache will be re-enabled
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Anna Dai authored
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DanielePettenuzzo authored
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DanielePettenuzzo authored
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- Feb 09, 2019
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Daniel Agar authored
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Daniel Agar authored
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- Feb 06, 2019
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Daniel Agar authored
- update navigator precision landing to build without multicopter
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- Feb 03, 2019
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Daniel Agar authored
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- Jan 30, 2019
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Daniel Agar authored
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